The present disclosure relates to the field of semiconductor chip fabrication. Still more particularly, the present disclosure relates to fabricating three-dimensional (3D) chips.
Early semiconductor logic chips, such as microprocessors, were fabricated in two dimensions (2D). That is, a single-layer chip would contain memory, execution units, busses, input/output (I/O) logic, and etc. all in a same plane. Recently developed logic chips, however, use a three-dimensional (3D) architecture, in which different components are physically on different chips. These different components typically interact via hard wiring, which causes timing and other signal problems. Furthermore, the 3D chip requires a different tapeout (final hardware design) for each layer. Thus, for a four layer 3D chip, four separate tapeouts are required. Validating a tapeout release and creating artwork (for photolithography used in the manufacturing of the chip) runs in the $1M-$2M range for 45 nm and newer technologies, thus resulting in a $4M-$8M tapeout expense for a four-layer 3D chip.